The present invention relates in general to phase lock loops and, more particularly, to a VCO power-up circuit for a PLL.
A conventional phase lock loop (PLL) generally includes a phase detector for monitoring a phase difference between a input reference signal and an output signal of a voltage controlled oscillator (VCO). The phase detector generates an UP control signal and a DOWN control signal for a charge pump to charge and discharge a loop filter at a loop node at the input of the VCO. The loop voltage developed across the loop filter determines the output frequency of the VCO. The UP and DOWN control signals driving the charge pump set the proper loop filter voltage at the input of the VCO to maintain a predetermined phase relationship between the signals applied to the phase detector.
PLLs are widely used for example in data communications, local area networks in computer applications, microprocessors and data storage applications to generate a clock signal having a known phase to control data transfers. A common problem related to PLL operation occurs during power-up where the power supply potential to the PLL has not yet reached full operating levels. With power supply potential below operational levels, any spurious noise in the input reference signal may cause the VCO to overshoot the reference frequency and result in catastrophic failure. Although the PLL may be restarted, the same problem is just as likely to reoccur while the circuit is powering up.
Hence, a need exists to prevent overshoot of the VCO and ensure stable power-up of the PLL until the power supply potential to the PLL reaches full operating levels.